As communication systems become more advanced the need for more efficient frequency generation becomes necessary. Frequency sources have been developed using techniques varying from complex mixing processes to digital synthesis. At the present time, attempts to design and construct fast hopping frequency sources are prevalent. One of the main building blocks in a fast hopping frequency source is a phase locked loop (PLL) circuit designed to step through a range of frequencies with a given increment.
A PLL circuit capable of stepping through a range of frequencies with a given increment generally includes a programmable frequency divider with consecutive integer division. Current techniques incorporate emitter controlled logic (ECL) modulus dividers and two or more counters in a pulse swallowing configuration to achieve consecutive integer division. The maximum operating frequency is approximately 600 MHz but the low value division (approximately 90) is sacrificed. Other designs make use of high frequency prescalers to reduce the input frequency. The problem with this technique is the loss of consecutive integer division. Because the frequencies in communications systems are continuously expanding into the higher bands of frequencies, it is necessary to increase the frequency response of the PLL and, hence, the programmable frequency divider therein. Unfortunately, higher frequency requires more power and a greater chip count.